ATM (Asynchronous Transfer Mode) is a packet switched and more specifically, cell switched broadband network technology. ATM forms the core of a broadband ISDN architecture that extends the digital transmission capabilities defined by ISDN for low rate voice, to voice and multimedia transmissions on the same lines.
ATM is a real time architecture that can provide very high bandwidth. Implementations currently operate at the speeds ranging from a special slow speed versions of 128 kbps up to 622.08 Mbps. Speeds as high as 2.488 Gbps will eventually be supported.
Because of the very high bandwidth, the ability to transmit multiple media data ATM can serve as an high speed architecture for both local area networks (LAN) and wide area networks (WAN).
ATM and AAL are associated with layer 2 of the OSI reference model.
The ATM layer is the service independent layer at which outgoing ATM cell headers and trailers are created, virtual channels and signal paths are defined and given unique identifiers, and cells are multiplexed or demultiplexed. The ATM layer creates the cells, then uses a physical layer to transmit them. Headers in received ATM cells are verified at this layer. Headers and trailers are also removed from incoming cells, the ATM layer is also responsible for traffic management.
The topmost layer is the AAL-layer (ATM Adaptation layer). The AAL-layer is service-dependent. It provides the necessary protocol translation between ATM and other communication services such as voice, video or data communication services involved in a transmission.
The AAL-layer has two sub-layers, i.e. the conversion sub-layer and the SAR-sub-layer. The conversion sub-layer provides the interface for the various services. The SAR-sub-layer (SAR: Segmentation and Re-assembly) is the sub-layer that packages variable size packages into fixed size cells at the transmitting end and re-packages the cells at the receiving end. The SAR-sub-layer is also responsible for finding and dealing with cells that are out of order or lost.
FIG. 1 shows an ATM node according to the state-of-the-art. The ATM node comprises several ATM-Port-Modules each comprising an ATM-controller unit. The ATM-controllers are linked via interfaces to an ATM switch device. Each ATM-Port-Module supports at least one physical transmission line (PHY). For XDSL up to 128 PHYs can be connected to the ATM-Port-Module. The ATM node can include cross connect without switching as well as true switching with signaling.
The number of ATM-Port-Modules within the ATM node is at least two. In a typical ATM node, several ATM-Port-Modules are provided. For instance, in a hub-system, up to 8 ATM-Port-Modules, in back-plane systems, up to 32 ATM-Port-Modules, and in large rack-based systems up to 256 ATM-Port-Modules are provided.
With the ATM-node according to the state-of-the-art as shown in FIG. 1, several problems arise. The production volume of the component for the ATM switch that forms the core module of the ATM node is much smaller than the production volume of the components for the ATM-Port-Modules by at least a factor of 10. A further significant problem is that there is no technical standard existent for the interconnection between the core module, i.e. and the ATM switch and the ATM-Port-Modules. In particular the ATM node according to the state-of-the-art as shown in FIG. 1 cannot be connected to an Ethernet network.
To overcome the production volume problem, an ATM node as shown in FIG. 2 has been developed by Transwitch (www.transwitch.com). This ATM node according to the state-of-the-art, as shown in FIG. 2, connects the ATM-Port-Modules of the ATM node via a passive cell bus. This proprietary back-plane bus or cell bus replaces the ATM switch within the ATM node. A disadvantage of the ATM node shown in FIG. 2 is that the cell bus limits the data throughput. The data throughput is limited by the cell bus of Transwitch to the maximum of about 1 Gbps. A further drawback is that the ATM node fails if one transmission line of the parallel cell bus is disconnected. A further major disadvantage is that the back-plane cell bus is also proprietary and not compatible to standard Ethernet systems.
FIG. 3 shows an ATM controller within an ATM-Port-Module according to the state-of-the-art. The ATM-controller performs the standard ATM-layer functions such as header detection and header translation. An ATM-OAM-processor performs OAM-functions (OAM: operation and maintenance) and traffic management functions in both directions. The ATM-header detector recognizes valid ATM-cell headers, i.e. by using predefined VPI/VCI-values (VPI: virtual path identifier; VCI: virtual channel identifier). Only a small subset of the large number of possible VPI/VCI-combinations are valid in a typical ATM-Port-Module. An ATM-header translation is performed before the ATM-cell leaves the ATM-controller. OAM-functions performed by the ATM-OAM-processors are i.e. loop back, performance monitoring and alarming. The OAM-functions are defined in the ITU-standard I. 610.
Traffic management functions are buffering of data streams and optionally policing, scheduling and traffic shaping. The traffic management functions of the ATM-controller are performed by buffering and scheduling devices. Policing is used to control the incoming cell streams. During the scheduling, an ensemble of connections with individual traffic parameters, either per connection or per group of connections, are selected and given opportunity to emit cells. Traffic-parameters are e.g. priority, minimum throughput, maximum burst size, cell loss rate. The traffic-parameters are assigned according to the information transported, e.g. real time voice, video data or non-real time data. Cell streams with the same destination are combined by the schedulers. In the signal path direction towards the ATM switch one scheduling device is assigned for each ATM-Port-Module, and in the opposite signal path direction at least one scheduler is assigned for each ATM-physical transmission line.
The ATM-OAM-processor and the buffering and scheduling devices are connected to a connection context memory within the ATM-controller. FIG. 4 shows a connection context memory according to the state-of-the-art. The ATM-header detector detects the header of an incoming ATM-cell and addresses an entry in a header lookup table. In the header lookup table, the outgoing header, port address P, OAM-parameter and a queue number Q are stored. The queue number Q serves as a pointer to a memory entry in the queue lookup table in which queue parameters are stored. The ATM switch receives enlarged ATM-cells with a prepended port address P that specifies the output port of the ATM-node.
FIG. 5a shows the data format of an ATM-cell having an ATM-header comprising 5 bytes and an ATM-payload comprising 48 bytes. FIG. 5b shows the data structure of an enlarged ATM-cell comprising a prepended port address P that indicates the destination port address in the node.
FIG. 5c shows the content of an ATM-cell according to the state-of-the-art. The ATM-cell consists of a 5 octet header in a 48 octet data or payload, section. Most of the bits in the ATM-header are used for virtual path and channel identification. The CLP (CLP: cell loss priority) bit indicates whether the cell can be discarded if the network traffic volume makes this advisable.
FIG. 5d shows the data structure of an Ethernet packet according to IEEE 802.3. The IEEE 802.3 standard is currently the most widely used architecture for local area networks (LAN). The frame sizes of the Ethernet packet shown in FIG. 5d varies between 64 and 1,518 data bytes. The Ethernet standard supports a wide range of transceiver types for communication over a given type of cabling. The most popular transceiver types are 10BASE5 (thick coax), 10BASE-T (two pair category 3,4,5 UTP [=unshielded twisted pair]), 100BASE-TX(two pair category 5 UTP), 100BASE-FX (dual multimode fiber), 1000BASE-T (four pairs category 5 UTP), 1000BASE-X (two optical fibers). The Ethernet frame comprises a preamble (7 bytes), a Start Frame Delimiter (SFD, 1 byte), the addresses of the frame's source and destination (each 6 bytes), a length or type field to indicate the length or protocol type of the following data field, a data field including padding if required (46-1500 bytes) and a Frame Check Sequence (FCS, 4 bytes) containing a cyclic redundant check (CRC) value to detect errors in the frame. Interpreting the type/length field as length or type distinguishes the two main types of Ethernet packets, i.e. Ethernet 2 and 802.3 based packets.
The payload of the Ethernet packet comprises 46-1,500 bytes of payload data. The payload data components must be at least 46 bytes and may include padding bytes.
As outlined above the ATM-nodes according to the state-of-the-art, as shown in FIGS. 1 and 2, are not compatible with Ethernet.